Dual data-rate (DDR) memory is a type of synchronized dynamic random access memory (DRAM) that supports data transfers on both edges of each clock cycle (the rising and falling edges), thereby effectively doubling the memory chip's data throughput. DDR memory consumes less power than conventional or single data-rate (SDR) memory, which makes it popular and well-suited for a wide variety of applications.
In a typical DDR memory, the memory array is arranged in multiple ranks. Each rank typically contains between four (4) and eighteen (18) unique DDR memory components. When a READ tenure is initiated to read data from a DDR memory component, the DDR memory uses a source-synchronous data strobe signal to deliver the data from the DDR memory component to the memory controller hub (MCH). That is, each DDR component has its own data strobe signal where the synchronization is provided by the individual memory module rather than the system clock of the MCH. However, the timing window for the data strobe signal and the arrival of the data can vary dramatically between different DDR memories. For example, one manufacturer may produce a DDR memory with a data strobe signal that has large timing window for the data strobe signal, while a different manufacture may produce a DDR memory with a small timing window for the data strobe signal.
Additionally, latency inherently exists between the time a read data request is made, i.e., the time data strobe signal is applied to the specified rank, and the time the read data becomes available on the DDR bus. This latency typically will vary between individual ranks within a given DDR memory. For example, all of the components within a given rank will have a specified latency while the components of another rank of the DDR memory will have a specified latency that is different from the latency of the other ranks. Furthermore, there are inherent time variations for reading data out between individual DDR components within a given rank.
Unfortunately, these variations in the timing window for the data strobe signal and between components of a given rank require large timing margins, which consume precious systems resources. The problem is further compounded in that many computer systems mix DDR memory modules from different manufacturers. Thus, the timing margins for the system must be large enough to accommodate the DDR memory with the largest timing window. If a DDR memory module is used that has better tolerances and requires a tighter timing window, system resources allocated for the timing margins are lost, which reduces the efficiency of the system and increases operating costs.
One solution to reduce the timing margins and increase system efficiency was to compensate for the latency between ranks within the DDR memory by applying a static DQS_OFFSET signal through the BIOS. Although the use of static DQS_OFFSET signals to compensate for the latency between ranks reduced the timing margins to a certain degree, the timing margins still had to be unduly large to accommodate for the latency between DDR memory modules made by varying manufactures. Furthermore, the static DQS_OFFSET signal could not account for the inherent latency between individual DDR components within a given rank. Although the use of static DQS_OFFSET signal reduced the timing margins to a certain degree, the timing margins associated with the DDR memories are still too large and consume too many system resources.
Therefore, there is a continuing need in the art for a method to improve DDR bus timing margins for READ tenures. In particular, there is a need for a method for adjusting the DDR bus timing margin to account for the variations